The present invention relates to reconfigurable logic chips.
Reconfigurable logic chips, such as field programmable gate arrays (FPGAs) have become increasingly popular. Such chips allow logic to implement different circuits at different times.
FPGAs are being increasingly used because they offer greater flexibility and shorter development cycles than traditional Application Specific Integrated Circuits (ASICs) while providing most of the performance advantages of a dedicated hardware solution.
One growingly popular use of FPGAs is referred to as reconfigurable computing. In reconfigurable computing, hardware logic functions are loaded into the FPGA as needed to implement different sections of a computationally intensive code. By using the FPGAs to do the computational intensive code, advantages are obtained over dedicated processors. Reconfigurable computing is being pursued by university researchers as well as FPGA companies.
Many FPGAs implement logic using lookup tables with feedback. These systems tend to be slow and inefficient especially for reconfigurable computing uses. It is desired to have an improved reconfigurable chip for reconfigurable computing.
The present invention concerns a reconfigurable chip in which the control and data paths are separated. In a reconfigurable computing environment, the control is the circuitry to set up the reconfigurable functional units. The data path is the path of the data through the different functional units.
By separating the control and the data path functions, the two systems can be separately optimized. For example, in the data path, the data typically moves linearly from one functional block to the next functional block. Interconnections of the data paths tend to have large numbers of short connections for a relatively large data groups. On the other hand, control systems tend to require fewer interconnections typically using cross-shaped or diagonal connections. The control interconnections tend to be random in nature. They are used to implement state machines and logic for decision management.
In a preferred environment of the present invention, control units include a state machine unit and a functional block configuration memory. Some output data bits from the state machine unit are sent to the functional block configuration memory as a configuration addresses. This configuration address is used by the functional block configuration memory to produce a configuration for the functional blocks (data path units) within the data path portion of the logic system.
This arrangement has a number of advantages. The functional block configuration memory preferably, for maximum efficiency, has a small number of address bits and a relatively large number of configuration lines. The configuration lines effectively produce the desired function for the functional blocks. Examples of functions implemented by the data path unit include add, subtract, shift, and compare. Since only a few bits are used for the address sent to the functional block configuration state memory, the sequencing state machine can be kept relatively small. The use of the state machine unit has the advantage that the state machine is very dense with a large number of interconnections. In a preferred environment, the state machine includes a reconfigurable programmable sum of products (PSOP) generator. In one embodiment, more than one functional block and functional block configuration memory can be connected to a single reconfigurable sum of product generator.
In a preferred embodiment, the reconfigurable sum of products generator stores multiple configurations that can be selectively loaded into the programmable sum of products generator. Data from the functional units can also be used to switch the configuration of the reconfigurable PSOP generator. By having a number of different configurations local at the chip, the operations done by the functional units can be quickly changed. This is particularly advantageous for some applications such as packet switching. For example, in a packet processing application, bits in certain fields of the packet can be interpreted by a functional unit implementing a compare function. If the bits are a certain value, the functional unit can produce a signal which causes a different configuration to be loaded into the reconfigurable programmable sum of products generator, thus implementing a different state machine. The system can continue operating without requiring a time-consuming load of a state machine configuration from an external memory when a backup configuration is stored locally.
Another embodiment of the present invention concerns the use of the reconfigurable programmable sum of products generator. The reconfigurable programmable sum of products generator structure is dense and highly interconnected and thus is advantageous for use in the control fabric of a reconfigurable chip. Additionally, by using a number of reconfigurable planes for the reconfigurable programmable sum of products generator, the programmable sum of products generator configurations can be quickly switched.